5 Terms
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Digital Signal Processors (DSP)
Industry: Semiconductors
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Digital Signal Processors (DSP)
pipelined-loop epilog
Semiconductors; Digital Signal Processors (DSP)
The portion of code that drains a pipeline in a software- pipelined loop. See also epilog.
FEA pipeline sequence
Semiconductors; Digital Signal Processors (DSP)
Fetch, execute, access pipeline sequence. The instruction-execution integer unit pipeline for the master processor. The fetch stage includes instruction and operand fetch; the execute stage includes ...
pipelined-loop prolog
Semiconductors; Digital Signal Processors (DSP)
The portion of code that primes the pipeline in a software-pipelined loop. See also prolog.
FR0/FR1
Semiconductors; Digital Signal Processors (DSP)
FIFO receive-interrupt bits. Bits within the synchronous serial port control register (SSPCR) which set an interrupt trigger condition based on the number of words in the receive FIFO buffer.
local data space
Semiconductors; Digital Signal Processors (DSP)
The portion of data-memory addresses that are not allocated as global by the global memory allocation register (GREG). If none of the data-memory addresses are allocated for global use, all of data ...
FT0/FT1
Semiconductors; Digital Signal Processors (DSP)
FIFO transmit-interrupt bits. Bits within the synchronous serial port control register (SSPCR) which set an interrupt trigger condition based on the number of words in the transmit FIFO buffer.
display area
Semiconductors; Digital Signal Processors (DSP)
The portion of the COMMAND window or parallel debug manager (PDM) window where the debugger/PDM echoes command entry, shows command output, and lists progress or error messages.
