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Digital Signal Processors (DSP)
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Digital Signal Processors (DSP)
next auxiliary register
Semiconductors; Digital Signal Processors (DSP)
The register that is pointed to by the auxiliary register pointer (ARP) when an instruction that modifies ARP is finished executing. See also auxiliary register; current auxiliary register.
urgent refresh cycles
Semiconductors; Digital Signal Processors (DSP)
High-priority refresh cycles that occur when the backlog of refresh requests exceeds 16. A burst of four refresh cycles is performed, with remaining refresh requests waiting for the completion of ...
runtime environment
Semiconductors; Digital Signal Processors (DSP)
The runtime parameters in which your program functions. These parameters are defined by the memory and register conventions, stack organization, function call conventions, and system initialization.
HOLDA
Semiconductors; Digital Signal Processors (DSP)
HOLD acknowledge signal. An output signal sent to the HOLDA pin by the CPU in acknowledgement of a properly initiated HOLD operation. When HOLDA is low, the processor is in a holding state and the ...
frame
Semiconductors; Digital Signal Processors (DSP)
The screen image output during a single vertical sweep.
contention
Semiconductors; Digital Signal Processors (DSP)
A situation where two or more devices or units attempt simultaneous accesses to the same resource.
resource table
Semiconductors; Digital Signal Processors (DSP)
A fixed-size table of pointers that the kernel uses to keep track of the internal resources it has opened or created. See also kernel resource.
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